1. Field of the Invention
The present invention relates to a MOS gate type semiconductor device having a MOS gate structure.
2. Description of the Related Art
In recent years, integrated circuits (ICs) in which a number of transistors and resistors are integrated to form electric circuits on one single chip are often used in significant parts of many computers, communication devices, and the likes. Among these ICs, such an IC which includes a high withstand voltage element is called a power IC.
A power IC integrates a drive circuit and a control circuit in itself, and application of a power IC has been proposed for various use, e.g., for use in a display drive device, a car mount IC, and the likes. Therefore, it is demanded that a high withstand voltage MOSFET (e.g., a lateral type MOSFET) used in an output stage of a power IC should have a high drain withstand voltage and a low ON-resistance.
FIG. 12 is a cross-section showing an element structure of a conventional lateral type MOSFET. In this figure, a reference 91 denotes a p-type semiconductor substrate, and an n-type source area 92 of high density (or low resistance) is selectively formed on the surface of the p-type semiconductor substrate 91.
In addition, an n-type drift region 93 of a low density (or high resistance) for ensuring a certain withstand voltage is selectively formed on the surface of the p-type semiconductor substrate 91, and an n-type drain region 94 of a high density is selectively formed on the surface of this n-type drift region 93.
A gate electrode 96 is provided on the p-type semiconductor substrate 91 between the n-type source region 92 and the n-type drift region 93, with a gate insulating film 95 inserted between the electrode 96 and the substrate 91o In addition, the n-type source region 92 is provided with a source electrode 97, and the source electrode 97 is in contact with both of the n-type source region 92 and the p-type semiconductor substrate 91. A drain electrode 98 is provided on the n-type drain region 94.
Meanwhile, the source-drain wiring pattern (SD wiring pattern) as a first layer in direct contact with source and drain regions is roughly classified into two kinds of patterns, i.e., a stripe wiring pattern and a mesh wiring pattern.
FIG. 13 is a plan view showing a stripe wiring pattern and FIG. 14 is a plan view showing a mesh wiring pattern.
The stripe wiring pattern is a pattern in which a linear source electrode 97, a linear gate electrode 96, and a linear drain electrode 98 are disposed alternately one after another, as shown in FIG. 13. In case of this stripe wiring pattern, the distance between a source electrode 97 and a drain electrode 98 is uniform.
On the other hand, the mesh pattern is a pattern in which source electrodes 96 and drain electrodes 98 are disposed in a matrix grid, which is surrounded by a gate electrode 96. In case of this mesh wiring pattern, the distance between a gate electrode 96 and a drain electrode 98 is not uniform. At several portions, this distance is longer than the distance in a stripe wiring pattern. However, since the drain electrode 98 is surrounded by the gate electrode, a gate electrode has of the mesh wiring pattern has a width greater than the stripe wiring pattern.
Thus, a stripe wiring pattern and a mesh wiring pattern are used as the SD wiring pattern as a first layer. However, when the size of each electrode is greater in comparison with the distance between the source and drain, the mesh pattern is rather effective. On the contrary, when the size of each electrode is small, the stripe wiring pattern is rather effective.
As has been described above, an n-type drift region 93 exists in a lateral type MOSFET element. The withstand voltage of the element is determined, depending on the impurity density of the n-type drift region 93 and the distance between a drain and a gate. To increase the withstand voltage, a drain region of a certain length is required. Therefore, in case of a lateral type MOSFET element, as the down-sizing of the element is proceeded, the stripe wiring pattern becomes more effective than the mesh wiring pattern.
Meanwhile, in case where the SD wiring pattern of as the first layer from the substrate is formed in a stripe wiring pattern, the SD wiring pattern of the second layer may be those wiring patterns which are shown in FIGS. 15 and 16. In these figures, the region indicated by oblique lines denotes a contact region between the SD wiring of the first layer and the SD wiring of the second layer, and the arrow denotes a current path.
The SD wiring pattern of the second layer in FIG. 15 is a pattern (a diagonal pattern) in which the lengthwise direction of source electrodes S.sub.2 and drain electrodes D.sub.2 is diagonal to the lengthwise direction of source electrodes S.sub.1 and drain electrodes D.sub.1.
Here, to decrease the resistance of the SD wiring of the second layer, the wiring width W.sub.2 may be increased. As the greater the wiring width W.sub.2 is, the larger the contact area between the SD wiring of the first layer and the SD wiring of the second layer is, and therefore, the smaller the contact resistance at the contact area is.
However, if the wiring width W.sub.2 is large, an effective distance between two adjacent contact regions is long. In other words, the current path between the contact region of the source wiring and the contact region of the drain wiring is long, and therefore, the contact resistance (i.e., the contact resistance of a first type) between contact regions equivalent a unit wiring width is increased.
For example, this state will be explained with reference to FIG. 17. FIG. 17 is a graph showing dependency of a wiring resistance on the wiring width W.sub.2 in a MOSFET using a diagonal wiring pattern. As shown in this figure, a broken line 110 indicating the wiring resistance of the second layer, the wiring resistance decreases in inverse proportion to the W.sub.2, while the wiring resistance increases in proportion to the W.sub.2 in case of a broken line 111 indicating the contact resistance of a first type. An actual wiring resistance is indicated by a continuous line 112 obtained by adding the broken lines 110 and 111 with each other. In case of this continuous line 112, the wiring width of the second layer increases in proportion to the W.sub.2, within a region where the W.sub.2 is small, and therefore, the wiring resistance decreases in inverse proportion to the W.sub.2. In case where the W.sub.2 is large, the effect that the length of a current path increases is prior to the effect that the contact area increases in proportion to the W.sub.2, and therefore, the wiring resistance increases in proportion to the W.sub.2.
Consequently, in case of a diagonal wiring pattern, there is a problem that the current path between the contact region of a source wiring and the contact region of a drain wiring is enlarged, and therefore, the contact resistance of the first type becomes high, if the wiring width W.sub.2 is large while the resistance of the SD wiring of the second layer is small.
On the other hand, the SD wiring pattern of the second layer in FIG. 16 is a pattern (i.e., a parallel wiring pattern) in which the lengthwise direction of its source electrodes S.sub.2 and drain electrodes D.sub.2 is parallel to the lengthwise direction of the lengthwise direction of the source electrodes S.sub.1 and drain electrodes D.sub.1 of the first layer.
In this case, since the contact area are between the SD wiring of the first layer and the SD wiring of the second layer is larger than in the case of FIG. 15, the contact resistance (i.e., the contact resistance of a second type) between the SD wiring of the first layer and the SD wiring of the second layer becomes much smaller.
However, the resistance of the SD wiring of the second layer is limited by the SD wiring of the first layer. Specifically, the wiring width W.sub.2 of the drain electrodes D.sub.2 (or source electrodes S.sub.2) of the second layer cannot be arranged to be larger than the twice of the distance between a drain electrode D.sub.1 and a source electrode S.sub.1 of the first layer, and therefore, the resistance of the SD wiring of the second SD wiring cannot be greatly decreased, unlike in the case of the diagonal wiring pattern shown in FIG. 15.
For example, this state will be explained with reference to FIG. 18. FIG. 18 is a graph showing a L.sub.2 dependency in a MOSFET using a parallel wiring pattern. The L.sub.2 denotes a overlapping width for which comb-like teeth of source and drain electrodes of the second layer are overlapped on each other. In addition, L denotes the pitch of a repeated pattern of the SD wiring of the second layer, and is here set to L=50 .mu.m. As shown in the figure, according to the broken line 120 indicating a case where the L.sub.2 is small, the wiring resistance decreases in proportion to the L.sub.2, while the wiring resistance increases in inverse proportion to the (L-L.sub.2) according to the broken line 121 indicating a case where the L.sub.2 is large. An actual wiring resistance is indicated by a continuous line 122 obtained by adding the broken lines 120 and 121 with each other. In case of this continuous line 122, within a region where the L.sub.2 is small, the current path between a drain electrode and a source electrode of the first layer is long, and therefore the resistance is relatively high. Within this region, since the current path becomes short in proportion to the L.sub.2, the wiring resistance decreases in proportion to the L.sub.2. In case where the L.sub.2 is large, since the value of (L-L.sub.2) in the drain electrodes and source electrodes of the second layer decreases in proportion to the L.sub.2, the wiring resistance increases together with the L.sub.2.
Consequently, in case of a parallel wiring pattern, there is a problem that the resistance of the SD wiring of the second layer cannot be decreased to be small although the contact resistance between the SD wiring of the first layer and the SD wiring of the second layer.
Thus, in a conventional high withstand voltage MOSFET, there is a problem that the contact resistance of the first and second types cannot be decreased to be small together with the resistance of the second layer.
On the other hand, as a wiring pattern other than a diagonal wiring pattern and a parallel wiring pattern, an oblique wiring pattern is disclosed in the Japanese Patent Application KOKAI Publication No. 1-112749, as long as a logic element having wirings of three or more layers is concerned. FIG. 19 schematically shows this oblique wiring pattern. This oblique wiring pattern consists of first layer wirings 131 formed in the longitudinal direction, second layer wirings 132 formed in the lateral direction, and third layer wirings 133 formed in an oblique direction such that the wirings 133 connects the cross points of the first and second layer wirings 131 and 132. The wiring layers are connected with each other through via-holes provided in the cross points.